SP

Sri Harsha POTHUKUCHI

CS Cadence Design Systems: 2 patents #23 of 250Top 10%
📍 San Jose, CA: #1,570 of 6,693 inventorsTop 25%
🗺 California: #13,721 of 66,859 inventorsTop 25%
Overall (2021): #110,677 of 548,734Top 25%
2
Patents 2021

Issued Patents 2021

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11188696 Method, system, and product for deferred merge based method for graph based analysis pessimism reduction Amit Dhuria, Pradeep Yadav, Pawan Kulshreshtha, Igor Keller, Sharad Mehrotra +2 more 2021-11-30
11003821 Deterministic loop breaking in multi-mode multi-corner static timing analysis of integrated circuits Amit Dhuria 2021-05-11