Issued Patents 2021
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11184097 | VLAN-aware clock hierarchy | Harold Fong, Petr Budnik | 2021-11-23 |
| 11070303 | Management message loop detection in precision time protocol | Avininderpal Singh Grewal, Petr Budnik | 2021-07-20 |