| 10872650 |
Ferroelectric memory cells |
Scott J. Derner |
2020-12-22 |
| 10867661 |
Main word line driver circuit |
Tae H. Kim |
2020-12-15 |
| 10861787 |
Memory device with bitline noise suppressing scheme |
Mitsunari Sukekawa |
2020-12-08 |
| 10854276 |
Apparatuses and methods including two transistor-one capacitor memory and for accessing same |
Scott J. Derner |
2020-12-01 |
| 10839871 |
Apparatuses and method for reducing sense amplifier leakage current during active power-down |
— |
2020-11-17 |
| 10825501 |
Pre-writing memory cells of an array |
Scott J. Derner |
2020-11-03 |
| 10796743 |
Dynamic adjustment of memory cell digit line capacitance |
Charles L. Ingalls, Scott J. Derner |
2020-10-06 |
| 10790000 |
Apparatuses and method for reducing row address to column address delay |
— |
2020-09-29 |
| 10706907 |
Cell-specific referenece generation and sensing |
Scott J. Derner |
2020-07-07 |
| 10672435 |
Sense amplifier signal boost |
Charles L. Ingalls |
2020-06-02 |
| 10636472 |
Boosting a digit line voltage for a write operation |
Howard C. Kirsch |
2020-04-28 |
| 10622057 |
Tri-level DRAM sense amplifer |
Charles L. Ingalls, Scott J. Derner |
2020-04-14 |
| 10607677 |
Cell-based reference voltage generation |
Scott J. Derner |
2020-03-31 |
| 10566043 |
Multi-level storage in ferroelectric memory |
— |
2020-02-18 |
| 10566036 |
Apparatuses and method for reducing sense amplifier leakage current during active power-down |
— |
2020-02-18 |
| 10559339 |
Periphery fill and localized capacitance |
Scott J. Derner |
2020-02-11 |
| 10541008 |
Apparatuses and methods for reducing row address to column address delay for a voltage threshold compensation sense amplifier |
Tae H. Kim |
2020-01-21 |
| 10535397 |
Sensing techniques for multi-level cells |
Scott J. Derner |
2020-01-14 |
| 10535399 |
Memory arrays |
Scott J. Derner |
2020-01-14 |
| 10529402 |
Ferroelectric memory cell sensing |
Scott J. Derner |
2020-01-07 |
