| 10831979 |
Time-driven placement and/or cloning of components for an integrated circuit |
Woohyun Chung, Lakshmi N. Reddy |
2020-11-10 |
| 10796064 |
Autonomous placement to satisfy self-aligned double patterning constraints |
Hua Xiang, Gustavo E. Tellez, Shyam Ramji |
2020-10-06 |
| 10762271 |
Model-based refinement of the placement process in integrated circuit generation |
Myung-Chul Kim, Shyam Ramji, Benjamin Neil Trombley, Paul G. Villarrubia |
2020-09-01 |
| 10719656 |
Triple and quad coloring of shape layouts |
Alexey Y. Lvov, Gustavo E. Tellez |
2020-07-21 |
| 10679120 |
Power driven synaptic network synthesis |
Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha |
2020-06-09 |
| 10635773 |
Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement |
Myung-Chul Kim, Paul G. Villarrubia, Shyam Ramji, Benjamin Neil Trombley |
2020-04-28 |
| 10606978 |
Triple and quad coloring of shape layouts |
Alexey Y. Lvov, Gustavo E. Tellez |
2020-03-31 |
| 10558775 |
Memory element graph-based placement in integrated circuit design |
Myung-Chul Kim, Arjen A. Mets, Shyam Ramji, Lakshmi N. Reddy, Alexander J. Suess +2 more |
2020-02-11 |
| 10552740 |
Fault-tolerant power-driven synthesis |
Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha |
2020-02-04 |
| 10534891 |
Time-driven placement and/or cloning of components for an integrated circuit |
Woohyun Chung, Lakshmi N. Reddy |
2020-01-14 |
| 10528695 |
Integer arithmetic method for wire length minimization in global placement with convolution based density penalty computation |
Alexey Y. Lvov, Benjamin Neil Trombley, Myung-Chul Kim, Paul G. Villarrubia |
2020-01-07 |
