Issued Patents 2020
Showing 25 most recent of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10878888 | Variable width memory module supporting enhanced error detection and correction | John Eric Linstadt, Kenneth L. Wright | 2020-12-29 |
| 10878878 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Lawrence Lai, Kishore Ven Kasamsetty | 2020-12-29 |
| 10878887 | Memory systems and methods for improved power management | James E. Harris | 2020-12-29 |
| 10860253 | Memory component having internal read-modify-write operation | Thomas Vogelsang | 2020-12-08 |
| 10847196 | Hybrid memory module | John Eric Linstadt, Kenneth L. Wright | 2020-11-24 |
| 10846252 | Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules | Ely Tsern, John Eric Linstadt, Thomas J. Giovannini, Kenneth L. Wright | 2020-11-24 |
| 10846006 | Adjustable access energy and access latency memory system and devices | John Eric Linstadt | 2020-11-24 |
| 10840974 | Transmitter/receiver with small-swing level-shifted output | Carl W. Werner | 2020-11-17 |
| 10838793 | Memory device with unidirectional error detection code transfer for both read and write data transmitted via bidirectional data link | Yuanlong Wang | 2020-11-17 |
| 10839884 | Memory component with efficient write operations | John Eric Linstadt, Brent Haukness, Kenneth L. Wright, Thomas Vogelsang | 2020-11-17 |
| 10831685 | Semiconductor memory systems with on-die data buffering | Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil | 2020-11-10 |
| 10825518 | Fast read speed memory device | Deepak C. Sekar, Gary B. Bronner | 2020-11-03 |
| 10817419 | Memory controller supporting nonvolatile physical memory | Ely Tsern | 2020-10-27 |
| 10819447 | Periodic calibration for communication channels by drift tracking | Craig E. Hampel, Richard E. Perego | 2020-10-27 |
| 10813216 | Load reduced memory module | Suresh Rajan | 2020-10-20 |
| 10812138 | Pseudo-differential signaling for modified single-ended interface | Carl W. Werner | 2020-10-20 |
| 10810139 | Memory access during memory calibration | Ian Shaeffer | 2020-10-20 |
| 10811062 | Deferred fractional memory row activation | James E. Harris, Thomas Vogelsang, Ian Shaeffer | 2020-10-20 |
| 10811080 | Memory component with pattern register circuitry to provide data patterns for calibration | Craig E. Hampel, Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern | 2020-10-20 |
| 10802981 | Techniques for storing data and tags in different memory arrays | — | 2020-10-13 |
| 10804139 | Semiconductor system | Ely Tsern, Ian Shaeffer | 2020-10-13 |
| 10795834 | Memory controller for selective rank or subrank access | Craig E. Hampel | 2020-10-06 |
| 10784868 | Low power logic circuitry | John Eric Linstadt | 2020-09-22 |
| 10771231 | Signaling system with adaptive timing calibration | Bret G. Stott, Craig E. Hampel | 2020-09-08 |
| 10762010 | Multi-mode memory module and memory component | John Eric Linstadt, Kenneth L. Wright | 2020-09-01 |