| 10839900 |
Parasitic voltage drop compensation in large cross-point arrays |
Seyoung Kim |
2020-11-17 |
| 10839292 |
Accelerated neural network training using a pipelined resistive processing unit architecture |
Yurii A. Vlasov |
2020-11-17 |
| 10832773 |
Architecture for enabling zero value shifting |
Seyoung Kim, Nanbo Gong, Wanki Kim |
2020-11-10 |
| 10831860 |
Alignment techniques to match symmetry point as zero-weight point in analog crosspoint arrays |
Seyoung Kim, Hyungjun Kim, Malte Johannes Rasch |
2020-11-10 |
| 10783432 |
Update management for RPU array |
Oguzhan Murat Onen |
2020-09-22 |
| 10755170 |
Resistive processing unit with hysteretic updates for neural network training |
Rudolf M. Tromp |
2020-08-25 |
| 10748064 |
Deep neural network training with native devices |
Seyoung Kim |
2020-08-18 |
| 10740671 |
Convolutional neural networks using resistive processing unit array |
— |
2020-08-11 |
| 10726895 |
Circuit methodology for differential weight reading in resistive processing unit devices |
Seyoung Kim, Hyung-Min Lee, Wilfried Haensch |
2020-07-28 |
| 10693736 |
Real time simulation monitoring |
Alain E. Biem, Bruce G. Elmegreen |
2020-06-23 |
| 10664745 |
Resistive processing units and neural network training methods |
Michael P. Perrone, Yurii A. Vlasov |
2020-05-26 |
| 10599744 |
Scalable architecture for analog matrix operations with resistive devices |
Seyoung Kim |
2020-03-24 |
