Issued Patents 2020
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10831965 | Placement of vectorized latches in hierarchical integrated circuit development | Harald D. Folberth | 2020-11-10 |
| 10831967 | Local clock buffer controller placement and connectivity | Jesse Peter Surprise, Gerald Strevig, III, Shawn Kollesar | 2020-11-10 |
| 10671791 | Dynamic microprocessor gate design tool for area/timing margin control | Arjen A. Mets, Lakshmi N. Reddy, Cindy S. Washburn, Nancy Y. Zhou | 2020-06-02 |
| 10606976 | Engineering change order aware global routing | Diwesh Pandey, Sven Peyer, Gustavo E. Tellez | 2020-03-31 |