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Computational memory cell and processing array device using memory cells |
Chao-Hung Chang, Avidan Akerib |
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Computational memory cell and processing array device with ratioless write port |
Patrick Chuang, Chao-Hung Chang |
2020-12-01 |
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Computational memory cell and processing array device using memory cells |
Chao-Hung Chang, Avidan Akerib |
2020-07-28 |
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Systems and methods involving multi-bank, dual-pipe memory circuitry |
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Systems and methods of pipelined output latching involving synchronous memory arrays |
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2020-01-14 |