Issued Patents 2020
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10839125 | Post-placement and post-routing physical synthesis for multi-die integrated circuits | Sreesan Venkatakrishnan, Ruibing Lu | 2020-11-17 |
| 10699053 | Timing optimization of memory blocks in a programmable IC | Zhiyong Wang, Ruibing Lu, Lin CHAI | 2020-06-30 |
| 10642951 | Register pull-out for sequential circuit blocks in circuit designs | Govinda Keshavdas, Anup Kumar Sultania, Chaithanya Dudha | 2020-05-05 |
| 10572621 | Physical synthesis within placement | Zhiyong Wang | 2020-02-25 |
| 10565334 | Targeted delay optimization through programmable clock delays | Ruibing Lu | 2020-02-18 |
| 10540463 | Placement of delay circuits for avoiding hold violations | Maheshwar Chandrasekar | 2020-01-21 |
| 10528697 | Timing-closure methodology involving clock network in hardware designs | Wei-Chun Chen, Xiaojian Yang | 2020-01-07 |