Issued Patents 2019
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10510847 | Transistor with source field plates under gate runner layers | Hiroyuki Tomomatsu, Hiroshi Yamasaki | 2019-12-17 |
| 10504885 | Electrostatic discharge guard ring with snapback protection | Sunglyong Kim, David LaFonteese, Seetharaman Sridhar | 2019-12-10 |
| 10468324 | Integration of heat spreader for beol thermal management | Archana Venugopal, Marie Denison, Luigi Colombo | 2019-11-05 |
| 10381456 | Group IIIA-N HEMT with a tunnel diode in the gate stack | Chang Soo Suh, Dong Seup Lee, Jungwoo Joh, Naveen Tipirneni | 2019-08-13 |
| 10347621 | Electrostatic discharge guard ring with snapback protection | Sunglyong Kim, David LaFonteese, Seetharaman Sridhar | 2019-07-09 |
| 10319809 | Structures to avoid floating resurf layer in high voltage lateral devices | Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott Balster +2 more | 2019-06-11 |
| 10312095 | Recessed solid state apparatuses | Dong Seup Lee, Yoshikazu Kondo, Pinghai Hao | 2019-06-04 |
| 10304719 | Deep trench isolation with tank contact grounding | Yongxi Zhang, Eugen Pompiliu Mindricelu, Seetharaman Sridhar | 2019-05-28 |
| 10290699 | Method for forming trench capacitor having two dielectric layers and two polysilicon layers | Hideaki Kawahara, Binghua Hu | 2019-05-14 |
| 10263085 | Transistor with source field plates and non-overlapping gate runner layers | Hiroyuki Tomomatsu, Hiroshi Yamasaki | 2019-04-16 |
| 10211335 | LDMOS transistor with segmented gate dielectric layer | Ming-Yeh Chuang | 2019-02-19 |
| 10205001 | Hybrid active-field gap extended drain MOS transistor | John Lin | 2019-02-12 |
| 10192799 | Method and apparatus to model and monitor time dependent dielectric breakdown in multi-field plate gallium nitride devices | Dong Seup Lee, Jungwoo Joh | 2019-01-29 |
| 10186589 | Transistor with source field plates under gate runner layers | Hiroyuki Tomomatsu, Hiroshi Yamasaki | 2019-01-22 |