Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10394718 | Slot/sub-slot prefetch architecture for multiple memory requestors | Joseph Zbiciak, Matthew D. Pierson | 2019-08-27 |
| 10311007 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Matthew D. Pierson | 2019-06-04 |