Issued Patents 2019
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10439628 | Top plate sampling circuit including input-dependent dual clock boost circuits | Neeraj Shrivastava, Arun Mohan | 2019-10-08 |
| 10425042 | Negative capacitance circuits including temperature-compensation biasings | Neeraj Shrivastava, Arun Mohan, Shagun Dusad | 2019-09-24 |
| 10396766 | Parasitic capacitance cancellation using dummy transistors | Basavaraj G. Gorguddi | 2019-08-27 |
| 10320405 | Pattern based estimation of errors in ADC | Srinivas Kumar Reddy Naru, Visvesvaraya Pentakota Appala, Shagun Dusad, Neeraj Shrivastava, Viswanathan Nagarajan +3 more | 2019-06-11 |