Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522459 | Method for fabricating semiconductor device having buried metal line | Tetsu Ohtou, Yusuke Oniki | 2019-12-31 |
| 10510739 | Method of providing layout design of SRAM cell | Tetsu Ohtou, Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen | 2019-12-17 |
| 10510403 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2019-12-17 |
| 10411019 | SRAM cell word line structure with reduced RC effects | Wei Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao | 2019-09-10 |
| 10354952 | Memory cell having multi-level word line | Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao | 2019-07-16 |
| 10354731 | Failure detection circuitry for address decoder for a data storage device | Ching-Wei Wu | 2019-07-16 |
| 10304527 | Semiconductor integrated circuit device | Makoto Yabuuchi | 2019-05-28 |
| 10276579 | Layout design for manufacturing a memory cell | Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen | 2019-04-30 |
| 10276231 | SRAM cell for interleaved wordline scheme | Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2019-04-30 |
| 10170413 | Semiconductor device having buried metal line and fabrication method of the same | Tetsu Ohtou, Yusuke Oniki | 2019-01-01 |