Issued Patents 2019
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10502784 | Voltage level monitoring of an integrated circuit for production test and debug | Satinder Singh Malhi | 2019-12-10 |
| 10495690 | Combinatorial serial and parallel test access port selection in a JTAG interface | Manish Sharma | 2019-12-03 |
| 10393804 | Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit | Nimit Endlay, Balwinder Singh Soni | 2019-08-27 |
| 10386411 | Sequential test access port selection in a JTAG interface | Manish Sharma | 2019-08-20 |
| 10228420 | Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit | Nimit Endlay, Balwinder Singh Soni | 2019-03-12 |