Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10338139 | Method and apparatus for scan chain reordering and optimization in physical implementation of digital integrated circuits with on-chip test compression | Guangyuan Kelvin Ge, Yu-Ming Chiang | 2019-07-02 |
| 10310013 | Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains | Guangyuan Kelvin Ge | 2019-06-04 |
| 10248750 | Power savings method in a clock mesh-based design through a smart decloning technique | Brian Millar, Suhail Ahmed | 2019-04-02 |