Issued Patents 2019
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10325058 | Method for verifying a layout designed for a semiconductor integrated circuit and a computer system for performing the same | JAEICK SON, Sunghoon Kim | 2019-06-18 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10325058 | Method for verifying a layout designed for a semiconductor integrated circuit and a computer system for performing the same | JAEICK SON, Sunghoon Kim | 2019-06-18 |