Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10505530 | Positive logic switch with selectable DC blocking circuit | Tero Tapio Ranta | 2019-12-10 |
| 10475720 | S-contact thermal structure with active circuitry | Tero Tapio Ranta | 2019-11-12 |
| 10438950 | S-contact for SOI | Befruz Tasbas, Alain Duvallet, Sinan Goktepeli | 2019-10-08 |
| 10389306 | Gate drivers for stacked transistor amplifiers | Poojan Wagh, Kashish Pal, Robert Mark Englekirk, Tero Tapio Ranta, Keith Bargroff | 2019-08-20 |
| 10367453 | Body tie optimization for stacked transistor amplifier | Chris Olson, Tero Tapio Ranta | 2019-07-30 |
| 10319854 | High voltage switching device | Abhijeet Paul, Alain Duvallet | 2019-06-11 |
| 10276371 | Managed substrate effects for stabilized SOI FETs | Robert Mark Englekirk, Keith Bargroff, Christopher C. Murphy, Tero Tapio Ranta | 2019-04-30 |
| 10236872 | AC coupling modules for bias ladders | Tero Tapio Ranta | 2019-03-19 |
| 10192884 | Butted body contact for SOI transistor | — | 2019-01-29 |