Issued Patents 2019
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10483241 | Semiconductor devices with through silicon vias and package-level configurability | James E. Davis, Warren L. Boyer | 2019-11-19 |
| 10453829 | Method and apparatus for reducing capacitance of input/output pins of memory device | Merri L. Carlson, Hongbin Zhu, Gordon A. Haller, James E. Davis, James Mathew +1 more | 2019-10-22 |
| 10403585 | Semiconductor devices with post-probe configurability | James E. Davis, Jeffrey P. Wright, Warren L. Boyer | 2019-09-03 |
| 10312232 | Semiconductor devices with package-level configurability | James E. Davis, John B. Pusey, Zhiping Yin | 2019-06-04 |
| 10283462 | Semiconductor devices with post-probe configurability | James E. Davis, Jeffrey P. Wright, Warren L. Boyer | 2019-05-07 |