| 10504585 |
Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers |
Yuniarto Widjaja, Zvi Or-Bach |
2019-12-10 |
| 10489245 |
Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them |
Neal Berger, Mourad El-Baraji, Lester Crudele |
2019-11-26 |
| 10481976 |
Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers |
Neal Berger, Mourad El-Baraji, Lester Crudele |
2019-11-19 |
| 10460781 |
Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2019-10-29 |
| 10446210 |
Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2019-10-15 |
| 10437491 |
Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2019-10-08 |
| 10437723 |
Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2019-10-08 |
| 10424393 |
Method of reading data from a memory device using multiple levels of dynamic redundancy registers |
Mourad El Baraji, Neal Berger, Lester Crudele, Daniel L. Hillman, Barry A. Hoberman |
2019-09-24 |
| 10395712 |
Memory array with horizontal source line and sacrificial bitline per virtual source |
Neal Berger, Mourad El Baraji, Lester Crudele |
2019-08-27 |
| 10395711 |
Perpendicular source and bit lines for an MRAM array |
Neal Berger, Mourad El Baraji, Lester Crudele |
2019-08-27 |
| 10373685 |
Content addressable memory device having electrically floating body transistor |
Jin-Woo Han, Yuniarto Widjaja |
2019-08-06 |
| 10366774 |
Device with dynamic redundancy registers |
Mourad El Baraji, Neal Berger, Lester Crudele, Daniel L. Hillman, Barry A. Hoberman |
2019-07-30 |
| 10366775 |
Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation |
Mourad El-Baraji, Neal Berger, Lester Crudele, Daniel L. Hillman, Barry A. Hoberman |
2019-07-30 |
| 10360964 |
Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2019-07-23 |
| 10360962 |
Memory array with individually trimmable sense amplifiers |
Susmita Karmakar, Neal Berger, Mourad El Baraji |
2019-07-23 |
| 10354718 |
Systems and methods for reducing standby power in floating body memory devices |
Yuniarto Widjaja |
2019-07-16 |
| 10332603 |
Access line management in a memory device |
Ali Mohammadzadeh, Aaron Yip |
2019-06-25 |
| 10236075 |
Predicting tunnel barrier endurance using redundant memory structures |
Kuk-Hwan Kim, Peter Cuevas, Amitay Levi |
2019-03-19 |
| 10192601 |
Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2019-01-29 |
| 10192872 |
Memory device having electrically floating body transistor |
Yuniarto Widjaja, Jin-Woo Han |
2019-01-29 |
| 10192602 |
Smart cache design to prevent overflow for a memory device with a dynamic redundancy register |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2019-01-29 |
| 10181471 |
Memory cell comprising first and second transistors and methods of operating |
Yuniarto Widjaja, Jin-Woo Han |
2019-01-15 |
