Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10489200 | Hierarchical staging areas for scheduling threads for execution | Olivier Giroux, Jack Choquette, Robert J. Stoll, Michael A. Fetterman | 2019-11-26 |
| 10459861 | Unified cache for diverse memory traffic | Ronny Meir Krashinsky, Steven James Heinrich, Shirish Gadre, John H. Edmondson, Jack Choquette +5 more | 2019-10-29 |
| 10255228 | System and method for performing shaped memory access operations | Jack Choquette, Manuel Gautho, Ming Y. Siu | 2019-04-09 |