Issued Patents 2019
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497409 | Implementing DRAM row hammer avoidance | Charles A. Kilmer, Anil B. Lingambudi, Diyanesh Babu C. Vidyapoornachary | 2019-12-03 |
| 10468088 | Redundant voltage regulator for memory devices | Brian J. Connolly, Kyu-hyoun Kim | 2019-11-05 |
| 10453503 | Implementing DRAM row hammer avoidance | Charles A. Kilmer, Anil B. Lingambudi, Diyanesh Babu C. Vidyapoornachary | 2019-10-22 |
| 10395698 | Address/command chip controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more | 2019-08-27 |
| 10353455 | Power management in multi-channel 3D stacked DRAM | Kevin M. Mcilvain, Saravanan Sethuraman, Kyu-hyoun Kim | 2019-07-16 |
| 10353669 | Managing entries in a mark table of computer memory errors | John S. Dodson, Marc A. Gollub, Brad W. Michael | 2019-07-16 |
| 10338999 | Confirming memory marks indicating an error in computer memory | John S. Dodson, Marc A. Gollub, Brad W. Michael | 2019-07-02 |
| 10304560 | Performing error correction in computer memory | John S. Dodson, Marc A. Gollub, Brad W. Michael | 2019-05-28 |
| 10297335 | Tracking address ranges for computer memory errors | John S. Dodson, Marc A. Gollub, Brad W. Michael | 2019-05-21 |
| 10281974 | Power management in multi-channel 3D stacked DRAM | Kevin M. Mcilvain, Saravanan Sethuraman, Kyu-hyoun Kim | 2019-05-07 |
| 10168923 | Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module | Edgar R. Cordero, Kyu-hyoun Kim, Adam J. McPadden, Anuwat Saetow | 2019-01-01 |