Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10224242 | Low-resistivity metallic interconnect structures | Chih-Chao Yang | 2019-03-05 |
| 10204823 | Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing | Stephen W. Bedell, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana | 2019-02-12 |