Issued Patents 2019
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10490740 | Non-volatile memory system with reliability enhancement mechanism and method of manufacture thereof | Shuichiro Yasuda, Dale W. Collins | 2019-11-26 |
| 10446751 | Methods of forming resistive memory elements | Christopher W. Petz, Yongjun Jeff Hu, D. V. Nirmal Ramaswamy | 2019-10-15 |
| 10431629 | Memory arrays and methods of forming an array of memory cells | Durai Vishak Nirmal Ramaswamy | 2019-10-01 |
| 10424481 | Methods of forming semiconductor device structures | Gurtej S. Sandhu | 2019-09-24 |
| 10408443 | Solid state lights with cooling structures | — | 2019-09-10 |
| 10411186 | Semiconductor devices including silver conductive materials | Sanh D. Tang, Whitney L. West, Rob B. Goodwin, Nishant Sinha | 2019-09-10 |
| 10410925 | Methods of forming integrated assemblies | Kurt D. Beigel | 2019-09-10 |
| 10388871 | Memory cells and methods of forming memory cells | Shuichiro Yasuda, Noel Rocklein, Durai Vishak Nirmal Ramaswamy, Qian Tao | 2019-08-20 |
| 10366983 | Semiconductor devices including control logic structures, electronic systems, and related methods | Kurt D. Beigel | 2019-07-30 |
| 10355002 | Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry | — | 2019-07-16 |
| 10340267 | Semiconductor devices including control logic levels, and related memory devices, control logic assemblies, electronic systems, and methods | Kurt D. Beigel | 2019-07-02 |
| 10333064 | Vertical memory cell for high-density memory | Gurtej S. Sandhu | 2019-06-25 |
| 10297290 | Semiconductor devices, and related control logic assemblies, control logic devices, electronic systems, and methods | Kurt D. Beigel | 2019-05-21 |
| 10283705 | Memory cells, semiconductor devices including the memory cells, and methods of operation | Timothy A. Quick, Eugene P. Marsh, Stefan Uhlenbrock, Chet E. Carter | 2019-05-07 |
| 10263183 | Methods of forming an array of cross point memory cells | Durai Vishak Nirmal Ramaswamy | 2019-04-16 |
| 10192873 | Memory cell, an array of memory cells individually comprising a capacitor and a transistor with the array comprising rows of access lines and columns of digit lines, a 2T-1C memory cell, and methods of forming an array of capacitors and access transistors there-above | Durai Vishak Nirmal Ramaswamy | 2019-01-29 |