| 10366954 |
Structure and method for flexible power staple insertion |
Juhan Kim, Navneet Jain |
2019-07-30 |
| 10360334 |
Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library |
Navneet Jain, Juhan Kim |
2019-07-23 |
| 10347543 |
FDSOI semiconductor device with contact enhancement layer and method of manufacturing |
Peter Baars, Rick Carter, Vikrant Chauhan, George Jonathan Kluth, Anurag Mittal +1 more |
2019-07-09 |
| 10340288 |
Method, apparatus, and system for improved memory cell design having unidirectional layout using self-aligned double patterning |
Juhan Kim |
2019-07-02 |
| 10333497 |
Calibration devices for I/O driver circuits having switches biased differently for different temperatures |
Anil Kumar, Sushama Davar, Navneet Jain |
2019-06-25 |
| 10303196 |
On-chip voltage generator for back-biasing field effect transistors in a circuit block |
Navneet Jain, Arif A. Siddiqi |
2019-05-28 |
| 10242946 |
Circuit design having aligned power staples |
Irene Y. Lin, Lei Yuan |
2019-03-26 |
| 10199378 |
Special construct for continuous non-uniform active region FinFET standard cells |
Navneet Jain, Juhan Kim, Andy T. Nguyen |
2019-02-05 |
