Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10387606 | Validating a clock tree delay | Jianquan Zheng | 2019-08-20 |
| 10354042 | Selectively reducing graph based analysis pessimism | Ritesh Shyamsukha, Shankar Radhakrishnan, Ted L. Craven | 2019-07-16 |