Issued Patents 2019
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10506139 | Reconfigurable pin-to-pin interface capable of supporting different lane combinations and/or different physical layers and associated method | Li-Hung Chiueh, Man-Ju Lee, Chen-Yu Hsiao | 2019-12-10 |
| 10453677 | Method of forming oxide layer | Cheng-Hsu Huang, Jui-Min Lee, Yi-Wei Chen, Wei-Hsin Liu, Shih-Fang Tzou | 2019-10-22 |
| 10446559 | Method of fabricating DRAM | Tzu-Chin Wu, Chao Liu, Yi-Wei Chen | 2019-10-15 |
| 10396806 | Voltage regulator based loop filter for loop circuit and loop filtering method | Ming Ting Wu | 2019-08-27 |
| 10387360 | Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver | Pin-Hao Feng, Yueh-Chuan Lu | 2019-08-20 |
| 10312080 | Method for forming amorphous silicon multuple layer structure | Mei-Ling Chen, Wei-Hsin Liu, Yi-Wei Chen, Jui-Min Lee, Chia-Lung Chang +2 more | 2019-06-04 |
| 10262895 | Method for forming semiconductor device | Mei-Ling Chen, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee +2 more | 2019-04-16 |
| 10263762 | Physical layer circuitry for multi-wire interface | Yuan-Hsun Chang, Yueh-Chuan Lu, Huai-Te Wang | 2019-04-16 |