CA

Charles J. Alpert

CS Cadence Design Systems: 12 patents #3 of 394Top 1%
IBM: 1 patents #5,496 of 11,143Top 50%
Overall (2019): #5,382 of 560,194Top 1%
13
Patents 2019

Issued Patents 2019

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
10460065 Routing topology generation using spine-like tree structure Wen-Hao Liu, Wing-Kai Chow, Gracieli Posser, Mehmet Can Yildiz, Zhuo Li 2019-10-29
10402533 Placement of cells in a multi-level routing tree William Robert Reece, Yi-Xiao Ding, Thomas Andrew Newton, Zhuo Li 2019-09-03
10402522 Region aware clustering Natarajan Viswanathan, Thomas Andrew Newton, William Robert Reece 2019-09-03
10380287 Systems and methods for modifying a balanced clock structure Dirk Meyer, Zhuo Li 2019-08-13
10354040 Systems and methods for clock tree generation with buffers and inverters Amin Farshidi, Thomas Andrew Newton, Zhuo Li 2019-07-16
10354183 Power-driven synthesis under latency constraints Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha, Gi-Joon Nam 2019-07-16
10318693 Balanced scaled-load clustering Natarajan Viswanathan, Zhuo Li, William Robert Reece, Thomas Andrew Newton 2019-06-11
10289797 Local cluster refinement Natarajan Viswanathan, Wen-Hao Liu, Thomas Andrew Newton 2019-05-14
10289795 Routing tree topology generation Jhih-Rong Gao, Thomas Andrew Newton, Derong Liu, Mehmet Can Yildiz, Zhuo Li 2019-05-14
10289775 Systems and methods for assigning clock taps based on timing Brian Wilson, Zhuo Li 2019-05-14
10282506 Systems and methods for clock tree clustering Dirk Meyer, Zhuo Li 2019-05-07
10216880 Systems and methods for power efficient flop clustering Wen-Hao Liu, Zhuo Li, Brian Wilson 2019-02-26
10198551 Clock cell library selection Amin Farshidi, Zhuo Li, William Robert Reece 2019-02-05