Issued Patents 2019
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10367516 | Jitter reduction techniques when using digital PLLs with ADCs and DACs | Frederick Carnegie Thompson, Varun Agrawal, Jose Barreiro Silva | 2019-07-30 |
| 10340926 | Fast settling sawtooth ramp generation in a phase-locked loop | Vamshi Krishna Chillara, Pablo Cruz Dato | 2019-07-02 |
| 10295580 | On-chip measurement for phase-locked loop | Vamshi Krishna Chillara, Pablo Cruz Dato | 2019-05-21 |