Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10268122 | Techniques to achieve area reduction through co-optimizing logic core blocks and memory redundancies | Abhik Ghosh, Niti Goel | 2019-04-23 |
| 10217732 | Techniques for forming a compacted array of functional cells | Rany T. Elsayed, Niti Goel, Randy J. Aksamit | 2019-02-26 |