Issued Patents 2019
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10521355 | Method, system, and apparatus for stress testing memory translation tables | Manoj Dusanapudi, Nelson Wu | 2019-12-31 |
| 10489261 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-11-26 |
| 10489259 | Replicating test case data into a cache with non-naturally aligned data boundaries | Manoj Dusanapudi | 2019-11-26 |
| 10482040 | Method, system, and apparatus for reducing processor latency | — | 2019-11-19 |
| 10481991 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-11-19 |
| 10438682 | List insertion in test segments with non-naturally aligned data boundaries | Manoj Dusanapudi, Nelson Wu | 2019-10-08 |
| 10417129 | Transactional memory operation success rate | — | 2019-09-17 |
| 10417131 | Transactional memory operation success rate | — | 2019-09-17 |
| 10346314 | Efficiently generating effective address translations for memory management test cases | Manoj Dusanapudi | 2019-07-09 |
| 10318456 | Validation of correctness of interrupt triggers and delivery | Manoj Dusanapudi, Brenton Yiu, Siva Sundar A | 2019-06-11 |
| 10261917 | Identifying stale entries in address translation cache | Vinod Bussa, Manoj Dusanapudi | 2019-04-16 |
| 10261878 | Stress testing a processor memory with a link stack | Manoj Dusanapudi | 2019-04-16 |
| 10241880 | Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems | Manoj Dusanapudi | 2019-03-26 |
| 10228422 | Driving pervasive commands using breakpoints in a hardware-accelerated simulation environment | Debapriya Chatterjee, John A. Schumann | 2019-03-12 |
| 10223225 | Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries | Manoj Dusanapudi | 2019-03-05 |
| 10185692 | Monitoring use of specialized hardware components (SHC) of processors in heterogeneous environments by storing event counts during execution | Grace Y. Liu, Karen Yokum | 2019-01-22 |
| 10169181 | Efficient validation of transactional memory in a computer processor | Vinod Bussa, Manoj Dusanapudi | 2019-01-01 |
| 10169186 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-01-01 |
| 10169185 | Efficient testing of direct memory address translation | Manoj Dusanapudi, Nelson Wu | 2019-01-01 |
| 10169180 | Replicating test code and test data into a cache with non-naturally aligned data boundaries | Manoj Dusanapudi | 2019-01-01 |