Issued Patents 2019
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10418094 | Predicting data correlation using multivalued logical outputs in static random access memory (SRAM) storage cells | Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann | 2019-09-17 |
| 10367520 | Charge-scaling subtractor circuit | Phil C. Paone, John E. Sheets, II, George Paulik, Karl R. Erickson, Gregory J. Uhlmann | 2019-07-30 |
| 10348320 | Charge-scaling adder circuit | Phil C. Paone, John E. Sheets, II, George Paulik, Karl R. Erickson, Gregory J. Uhlmann | 2019-07-09 |
| 10304522 | Method for low power operation and test using DRAM device | Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann | 2019-05-28 |
| 10236887 | Generating a unique die identifier for an electronic chip | Karl R. Erickson, Phil C. Paone, John E. Sheets, II, Gregory J. Uhlmann | 2019-03-19 |
| 10236050 | Optimizing data approximation analysis using low power circuitry | Karl R. Erickson, Phil C. Paone, George Paulik, John E. Sheets, II, Gregory J. Uhlmann | 2019-03-19 |
| 10224410 | Through-substrate via power gating and delivery bipolar transistor | Gerald K. Bartley, John E. Sheets, II | 2019-03-05 |
| 10224089 | Optimizing data approximation analysis using low bower circuitry | Karl R. Erickson, Phil C. Paone, George Paulik, John E. Sheets, II, Gregory J. Uhlmann | 2019-03-05 |
| 10170578 | Through-substrate via power gating and delivery bipolar transistor | Gerald K. Bartley, John E. Sheets, II | 2019-01-01 |