Issued Patents 2019
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522555 | Semiconductor devices including Si/Ge active regions with different Ge concentrations | Gunter Grasshoff, Carsten Peters | 2019-12-31 |
| 10483154 | Front-end-of-line device structure and method of forming such a front-end-of-line device structure | Marcus Wolf, Carsten Peters, Markus Lenski, Loic Gaben | 2019-11-19 |
| 10418380 | High-voltage transistor device with thick gate insulation layers | Nigel Chan, Nilesh Kenkare | 2019-09-17 |
| 10396084 | Semiconductor devices including self-aligned active regions for planar transistor architecture | Nigel Chan, Nilesh Kenkare, Hongsik Yoon | 2019-08-27 |
| 10340359 | Gate structure with dual width electrode layer | — | 2019-07-02 |
| 10319827 | High voltage transistor using buried insulating layer as gate dielectric | Nigel Chan | 2019-06-11 |
| 10304683 | Early gate silicidation in transistor elements | — | 2019-05-28 |
| 10283365 | Technique and related semiconductor devices based on crystalline semiconductor material formed on the basis of deposited amorphous semiconductor material | — | 2019-05-07 |
| 10199259 | Technique for defining active regions of semiconductor devices with reduced lithography effort | Michael Zier | 2019-02-05 |
| 10177163 | SOI-based floating gate memory cell | Nigel Chan | 2019-01-08 |