VR

Vasant Ramabadran

CS Cadence Design Systems: 2 patents #48 of 394Top 15%
📍 San Jose, CA: #1,646 of 6,652 inventorsTop 25%
🗺 California: #14,923 of 67,890 inventorsTop 25%
Overall (2019): #109,738 of 560,194Top 20%
2
Patents 2019

Issued Patents 2019

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10489534 Support for multiple user defined assertion checkers in a multi-FPGA prototyping system — 2019-11-26
10282501 Support for multiple user defined assertion checkers in a multi-FPGA prototyping system — 2019-05-07