Issued Patents 2019
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10416232 | Timing optimizations in circuit designs using opposite clock edge triggered flip-flops | Guenter Stenz | 2019-09-17 |
| 10318699 | Fixing hold time violations using hold time budgets and slacks of setup times | Satish B. Sivaswamy | 2019-06-11 |