Issued Patents 2018
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10074420 | Access signal adjustment circuits and methods for memory cells in a cross-point array | Christophe J. Chevallier | 2018-09-11 |
| 10031686 | Array voltage regulating technique to enable data operations on large memory arrays with resistive memory elements | — | 2018-07-24 |
| 10002646 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays | Christophe J. Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala | 2018-06-19 |
| 9997241 | High voltage switching circuitry for a cross-point array | Christophe J. Chevallier | 2018-06-12 |
| 9959078 | Multi-die rolling status mode for non-volatile storage | Grishma Shah, Jack Edward Frayer, Aaron K. Olbrich, Vidyabhushan Mohan, Gopinath Balakrishnan +1 more | 2018-05-01 |
| 9905307 | Leakage current detection in 3D memory | Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Gopinath Balakrishnan, Kapil Verma | 2018-02-27 |
| 9870809 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory | Christophe J. Chevallier, Seow Fong Lim | 2018-01-16 |
| 9870823 | Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations | Bruce L. Bateman | 2018-01-16 |