Issued Patents 2018
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10062768 | Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout | Ukjin Roh, Shashank S. Ekbote | 2018-08-28 |
| 9953967 | Integrated circuit with dual stress liner boundary | Greg Baldwin | 2018-04-24 |
| 9922971 | Integration of analog transistor | Himadri Sekhar Pal, Shashank S. Ekbote | 2018-03-20 |
| 9882051 | Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions | Ukjin Roh, Shashank S. Ekbote | 2018-01-30 |