| 10162641 |
Highly integrated scalable, flexible DSP megamodule architecture |
Timothy David Anderson, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more |
2018-12-25 |
| 10083035 |
Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization |
Timothy David Anderson |
2018-09-25 |
| 10078551 |
Streaming engine with error detection, correction and restart |
Timothy David Anderson |
2018-09-18 |
| 10073696 |
Streaming engine with cache-like stream data storage and lifetime tracking |
— |
2018-09-11 |
| 10061675 |
Streaming engine with deferred exception reporting |
Timothy David Anderson, Duc Quang Bui, Kai Chirca |
2018-08-28 |
| 10037439 |
Secure master and secure guest endpoint security firewall |
Timothy David Anderson, Matthew D. Pierson, Kai Chirca |
2018-07-31 |
| 10007518 |
Register file structures combining vector and scalar data with global and local accesses |
Timothy David Anderson, Duc Quang Bui, Mel Alan Phipps, Todd T. Hahn |
2018-06-26 |
| 9965395 |
Memory attribute sharing between differing cache levels of multilevel cache |
Raguram Damodaran, Naveen Bhoria |
2018-05-08 |
| 9965278 |
Streaming engine with compressed encoding for loop circular buffer sizes |
— |
2018-05-08 |
| 9904645 |
Multicore bus architecture with non-blocking high performance transaction credit system |
David Matthew Thompson, Timothy David Anderson, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson |
2018-02-27 |
| 9898415 |
Slot/sub-slot prefetch architecture for multiple memory requestors |
Kai Chirca, Matthew D. Pierson |
2018-02-20 |