Issued Patents 2018
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140407 | Method, device and computer program product for integrated circuit layout generation | Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Ke-Ying Su, Wen-Hao Chen +1 more | 2018-11-27 |
| 10019548 | Method of generating modified layout and system therefor | Ke-Ying Su, Hsien-Hsin Sean Lee | 2018-07-10 |
| 9922162 | Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout | C. Y. Chen, Hsiu-Wen Hsueh, Jun Huang, Shao-Heng Chou | 2018-03-20 |