Issued Patents 2018
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9990453 | Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness | Jean-Marc A. Forey, Mahantesh D. Narwade, Horia Alexandru Toma | 2018-06-05 |
| 9886753 | Verification of circuit structures including sub-structure variants | Mahantesh D. Narwade, Kaushik De, Rajarshi Mukherjee, Suman Nandan, Subhamoy Pal | 2018-02-06 |