Issued Patents 2018
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140415 | Method and system for verifying layout of integrated circuit including vertical memory cells | Jae Eun Lee, Sung Hoon Kim, Jae Ick SON | 2018-11-27 |
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140415 | Method and system for verifying layout of integrated circuit including vertical memory cells | Jae Eun Lee, Sung Hoon Kim, Jae Ick SON | 2018-11-27 |