Issued Patents 2018
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162554 | System and method for controlling a programmable deduplication ratio for a memory system | Krishna T. Malladi, Dimin Niu | 2018-12-25 |
| 10157657 | Selective refresh with software components | James Tringali, Frederick A. Ware | 2018-12-18 |
| 10133676 | Cache memory that supports tagless addressing | Trung Diep | 2018-11-20 |
| 10114560 | Hybrid memory controller with command buffer for arbitrating access to volatile and non-volatile memories in a hybrid memory group | Dimin Niu, Mu-Tien Chang, Sun-Young Lim, Indong Kim | 2018-10-30 |
| 10102140 | Methods and apparatuses for addressing memory caches | Trung Diep | 2018-10-16 |
| 10101935 | System and method for providing expandable and contractible memory overprovisioning | Krishna T. Malladi | 2018-10-16 |
| 10073790 | Electronic system with memory management mechanism and method of operation thereof | Krishna T. Malladi | 2018-09-11 |
| 10049717 | Wear leveling for storage or memory device | Dimin Niu, Mu-Tien Chang, Kyung-Chang Ryoo | 2018-08-14 |
| 10013212 | System architecture with memory channel DRAM FPGA module | Mu-Tien Chang | 2018-07-03 |
| 10002043 | Memory devices and modules | Chaohong Hu, Liang Yin, Uksong Kang | 2018-06-19 |
| 10002044 | Memory devices and modules | Chaohong Hu, Uksong Kang, Zhan Ping | 2018-06-19 |
| 9996390 | Method and system for performing adaptive context switching | Suhas | 2018-06-12 |
| 9983821 | Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application | Frederic Sala, Chaohong Hu, Dimin Niu, Mu-Tien Chang | 2018-05-29 |
| 9971511 | Hybrid memory module and transaction-based memory interface | Dimin Niu, Mu-Tien Chang | 2018-05-15 |
| 9966152 | Dedupe DRAM system algorithm architecture | Chaohong Hu, Krishna T. Malladi, Bob Brennan | 2018-05-08 |
| 9954533 | DRAM-based reconfigurable logic | Mingyu Gao, Krishna T. Malladi | 2018-04-24 |
| 9934154 | Electronic system with memory management mechanism and method of operation thereof | Krishna T. Malladi, Uksong Kang | 2018-04-03 |
| 9922696 | Circuits and micro-architecture for a DRAM-based processing unit | Shaungchen Li, Dimin Niu, Krishna T. Malladi | 2018-03-20 |
| 9916091 | Memory system architecture | Suhas, Chaohong Hu | 2018-03-13 |
| 9910775 | Computing system with adaptive back-up mechanism and method of operation thereof | Keith Chan, Wonseok Lee, Tackhwi Lee | 2018-03-06 |
| 9904635 | High performance transaction-based memory systems | Mu-Tien Chang, Liang Yin | 2018-02-27 |
| 9886194 | NVDIMM adaptive access mode and smart partition mechanism | Dimin Niu | 2018-02-06 |