Issued Patents 2018
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10162772 | Clock generation for timing communications with ranks of memory devices | Ian Shaeffer, John Eble | 2018-12-25 |
| 10135647 | Methods and circuits for asymmetric distribution of channel equalization between devices | Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin | 2018-11-20 |
| 10135427 | Receiver with time-varying threshold voltage | Brian S. Leibowitz, Qi Lin | 2018-11-20 |
| 10108246 | Using dynamic bursts to support frequency-agile memory interfaces | Brian Hing-Kit Tsang, Barry William Daly | 2018-10-23 |
| 10103907 | Selectable-tap equalizer | Vladimir Stojanovic, Fred F. Chen | 2018-10-16 |
| 10056384 | Multi-die fine grain integrated voltage regulation | Emerson S. Fang, Jun Zhai, Shawn Searles | 2018-08-21 |
| 10003484 | High-speed signaling systems with adaptable pre-emphasis and equalization | Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton, Kevin S. Donnelly +1 more | 2018-06-19 |
| 9998305 | Multi-PAM output driver with distortion compensation | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos +2 more | 2018-06-12 |
| 9973177 | Clock generator with injection-locking oscillators | Yue Lu | 2018-05-15 |
| 9923711 | Low power edge and data sampling | — | 2018-03-20 |
| 9917708 | Partial response receiver | Vladimir Stojanovic, Andrew Ho, Anthony Bessios, Bruno W. Garlepp, Grace Tsang +2 more | 2018-03-13 |
| 9912469 | Phase control block for managing multiple clock domains in systems with frequency offsets | Hae-Chang Lee, Carl W. Werner | 2018-03-06 |
| 9900189 | Methods and circuits for asymmetric distribution of channel equalization between devices | Fariborz Assaderaghi, Brian S. Leibowitz, Hae-Chang Lee, Jihong Ren, Qi Lin | 2018-02-20 |
| 9893720 | Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid | Brian Hing-Kit Tsang | 2018-02-13 |