Issued Patents 2018
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10120800 | History based memory speculation for partitioned cache memories | Ramaswamy Sivaramakrishnan, Serena Leung | 2018-11-06 |
| 10007629 | Inter-processor bus link and switch chip failure recovery | Thomas M. Wicki, Sumti Jairath, Kathirgamar Aingaran, Ali Vahidsafa, Paul N. Loewenstein | 2018-06-26 |
| 9892039 | Non-temporal write combining using cache resources | Mark Luttrell, Ramaswamy Sivaramakrishnan, Serena Leung | 2018-02-13 |