Issued Patents 2018
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10141056 | Memories including multiple arrays of non-volatile memory cells selectively connected to sense circuitry using different numbers of data lines | Peter Feeley | 2018-11-27 |
| 10090053 | Apparatus, systems, and methods to operate a memory | Takehiro Hasegawa, Mark A. Helm | 2018-10-02 |
| 10090052 | Sequential write and sequential write verify in memory device | — | 2018-10-02 |
| 10090024 | Memory device including current generator plate | — | 2018-10-02 |
| 10079065 | Reduced voltage nonvolatile flash memory | — | 2018-09-18 |
| 10074431 | 3D NAND memory Z-decoder | — | 2018-09-11 |
| 10074430 | Multi-deck memory device with access line and data line segregation between decks and method of operation thereof | — | 2018-09-11 |
| 10049750 | Methods including establishing a negative body potential in a memory cell | Mark Hawes, Toru Tanzawa, Jeremy Binfet | 2018-08-14 |
| 10042755 | 3D vertical NAND memory device including multiple select lines and control lines having different vertical spacing | — | 2018-08-07 |
| 10020056 | Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor | — | 2018-07-10 |
| 10014053 | Methods for backup sequence using three transistor memory cell devices | Peter Feeley | 2018-07-03 |
| 9972391 | Apparatus, systems, and methods to operate a memory | Takehiro Hasegawa, Mark A. Helm | 2018-05-15 |
| 9934868 | Methods and apparatuses having strings of memory cells and select gates with double gates | — | 2018-04-03 |
| 9881674 | Sequential write and sequential write verify in memory device | — | 2018-01-30 |
| 9881686 | Apparatuses and methods to control body potential in 3D non-volatile memory operations | Han Zhao, Akira Goda, Krishna K. Parat, Aurelio Giancarlo Mauri, Haitao Liu +2 more | 2018-01-30 |
| 9865311 | Memory device including current generator plate | — | 2018-01-09 |