JZ

Jiangli Zhu

VT Via Technologies: 4 patents #5 of 43Top 15%
📍 San Jose, CA: #604 of 5,991 inventorsTop 15%
🗺 California: #4,911 of 60,411 inventorsTop 9%
Overall (2018): #42,938 of 503,207Top 9%
4
Patents 2018

Issued Patents 2018

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
10141953 Low-density parity-check apparatus and matrix trapping set breaking method Ying Yu Tai 2018-11-27
10055288 Controller device and operation method for non-volatile memory with 3-dimensional architecture Ying Yu Tai, Jiin Lai 2018-08-21
10049007 Non-volatile memory device and read method thereof Ying Yu Tai 2018-08-14
10050643 Low-density parity-check apparatus and operation method thereof Ying Yu Tai 2018-08-14