Sheng Ye — 10 Patents at Maxlinear

Issued Patents 2018

Showing 1–10 of 10 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
10148417	Duty-cycled high speed clock and data recovery with forward error correction assist	Curtis Ling	2018-12-04	$4,419,000
10103822	Transceiver array	Curtis Ling	2018-10-16	$2,053,000
10097193	Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation	Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Timothy Gallagher	2018-10-09	$2,122,000
10072135	Compositions including a polythiol, an unsaturated compound, and a dye and methods relating to such compositions	Kathleen S. Shafer, Michael S. Wendland, Jonathan D. Zook, Susan E. DeMoss	2018-09-11	$33,610,000
10063906	Method and system for multi-path video and network channels	Anand Anandakumar, Curtis Ling	2018-08-28	$2,865,000
10063266	Method and system for a baseband cross-bar	Raja Pullela, Morten Damgaard	2018-08-28	$2,865,000
10014888	Jitter improvement in serializer-deserializer (SerDes) transmitters	Amir Hadji-Abdolhamid	2018-07-03	$5,278,000
10003347	Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs)	Eric Fogleman, Xuefeng Chen, Kok Lim Chan	2018-06-19	$3,433,000
9974025	Channel-sensitive power control	James Qiu, Sridhar Ramesh, Curtis Ling	2018-05-15	$6,033,000
9906227	Method and system for a sampled loop filter in a phase locked loop (PLL)	Sangeetha Gopalakrishnan, Vamsi Paidi	2018-02-27	$2,985,000