CI

Chung-Wah Norris Ip

CS Cadence Design Systems: 3 patents #4 of 223Top 2%
📍 Cupertino, CA: #222 of 1,457 inventorsTop 20%
🗺 California: #7,478 of 60,411 inventorsTop 15%
Overall (2018): #80,456 of 503,207Top 20%
3
Patents 2018

Issued Patents 2018

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
10162917 Method and system for implementing selective transformation for low power verification Fabiano Peixoto, Benjamin Chen, Björn Håkan Hjort 2018-12-25
10094875 Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design Chien-Liang Lin, Andrea Iabrudi Tavares 2018-10-09
9928328 Method and system for automated debugging of a device under test Ynon Cohen, Tal Tabakman, Yonatan Ashkenazi, Nadav Chazan, Gavriel Leshem 2018-03-27