Issued Patents 2018
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10031988 | Model order reduction in transistor level timing | Yanai Danan, Vasant Rao, Jeffrey P. Soreff, Xin Zhao | 2018-07-24 |
| 9886541 | Process for improving capacitance extraction performance | Susan E. Cellier, Lewis W. Dewey, III, Anthony D. Hagin, Adam P. Matheny, Ronald D. Rose +1 more | 2018-02-06 |