Issued Patents 2018
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10147733 | Method for forming a PN junction and associated semiconductor device | Stephan Niel, Arnaud Regnier | 2018-12-04 |
| 10147490 | Method for reducing a memory operation time in a non-volatile memory device and corresponding non-volatile memory device | Francesca Grande, Gianbattista Lo Giudice, Giovanni Matranga | 2018-12-04 |
| 10128314 | Vertical bipolar transistor | Philippe Boivin, Julien Delalleau | 2018-11-13 |
| 10127966 | Reading circuit with a shifting stage and corresponding reading method | Antonino Conte, Enrico Castaldo, Raul Andres Bianchi | 2018-11-13 |
| 10083753 | Method for managing a fail row of the memory plane of a non volatile memory and corresponding memory device | Gineuve Alieri | 2018-09-25 |
| 10038372 | Method and device for controlling a charge pump circuit | Paola Cavaleri | 2018-07-31 |
| 10002906 | Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device | Stephan Niel, Arnaud Regnier | 2018-06-19 |
| 9997213 | Sense amplifier | Gineuve Alieri | 2018-06-12 |
| 9984770 | Method for managing a fail bit line of a memory plane of a non volatile memory and corresponding memory device | Gineuve Alieri | 2018-05-29 |
| 9941369 | Memory cell comprising non-self-aligned horizontal and vertical control gates | Stephan Niel, Julien Delalleau, Arnaud Regnier | 2018-04-10 |
| 9941012 | Twin memory cell interconnection structure | Stephan Niel, Arnaud Regnier | 2018-04-10 |
| 9941010 | Non-volatile memory with a variable polarity line decoder | — | 2018-04-10 |
| 9875798 | Method for managing a fail row of the memory plane of a non volatile memory and corresponding memory device | Gineuve Alieri | 2018-01-23 |
| 9876122 | Vertical memory cell with non-self-aligned floating drain-source implant | Marc Mantelli, Stephan Niel, Arnaud Regnier, Julien Delalleau | 2018-01-23 |