Issued Patents 2018
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10142089 | Baud-rate clock data recovery with improved tracking performance | Yuhan Yao, Xun Zhang, Jianghui Su, Muthukumar Vairavan, Chaitanya Palusa | 2018-11-27 |
| 10129121 | Clock circuit jitter calibration | Philip P. Kwan | 2018-11-13 |
| 10122174 | Parallelization method for black-start subsystems of power grid with external support | Jingyou Xu, Qing Chang, Chunming Wang, Hanping Xu, Youping Xu +2 more | 2018-11-06 |
| 10084591 | SERDES built-in sinusoidal jitter injection | Chaitanya Palusa, Jiangyuan Li, Pradeep Nagarajan | 2018-09-25 |
| 9921899 | Monitoring serial link errors | Michelle Wong, Thomas M. Wicki, Albert Martin | 2018-03-20 |
| 9917607 | Baseline wander correction gain adaptation | Xun Zhang, Jianghui Su, Chaitanya Palusa | 2018-03-13 |
| 9893878 | On-chip jitter measurement for clock circuits | Long Kong, Ben Li Chen, Philip P. Kwan, Zuxu Qin | 2018-02-13 |